As an integrated circuit memory device, a flash memory has a function of storing information which is electrically erasable. Therefore, flash memory is widely used in electronic products, such as laptops, mobile phones, digital music players and etc. According to different gate structures, flash memories are generally classified into two types: stacked-gate flash memories and split-gate flash memories, in which memory units are required to be arranged in an array for proper operation and each memory unit is used to store a single bit of data. In such a memory array, a field oxide layer or a trench insulator layer is used to separate memory units. Meanwhile, in order to improve the programming efficiency of the flash memory, memory units are designed to occupy a large area, so as to obtain a high capacitance coupling ratio. However, the memory units of flash memory having a relatively large area may reduce the storage density.
In order to improve the storage density of flash memory, a dual-bit split gate flash memory is provided. FIG. 1 illustrates a schematic structure diagram of a conventional dual-bit split gate flash memory array and a row decoding circuit thereof. Referring to FIG. 1, the dual-bit split gate flash memory array includes a plurality of memory units (e.g., the memory unit M) arranged in an array, a plurality of bit lines (BL1, BL2, BL3, . . . , BLn), a plurality of word lines (WL1, WL2, . . . , WLm) and a plurality of control-gate lines (CG1 and CG2, CG3 and CG4, . . . , CG2m-1 and CG2m). The plurality of bit lines, the plurality of word lines and the plurality of control-gate lines are used to select a memory unit and to provide a drive signal. The memory unit has a dual-bit split gate flash transistor structure. Each memory unit includes two memory bits: a first memory bit and a second memory bit, and a middle electrode shared by the two memory bits. Each memory bit includes a bit line electrode and a control-gate electrode. Each memory unit is connected to two adjacent bit lines. Namely, the bit line electrode of the first memory bit and the bit line electrode of the second memory bit are connected to the two adjacent bit lines, respectively. For example, the memory unit M includes a first memory bit C1 and a second memory bit C2. A middle electrode shared by the first memory bit C1 and the second memory bit C2 is connected to the word line WL1. The bit line electrode of the first memory bit C1 is connected to the bit line BL3, and the control-gate electrode of the first memory bit C1 is connected to control-gate line CG1. The bit line electrode of the second memory bit C2 is connected to the bit line BL2, and the control-gate electrode of the second memory bit is connected to the control-gate line CG2.
When a reading or writing operation is performed on the dual-bit split gate flash memory shown in FIG. 1, the row decoding circuit provides a word line operation voltage and a control-gate operation voltage to a selected memory unit. In the prior art, memory units in a same row corresponds to a same row decoding unit. For example, the dual-bit split gate flash memory array shown in FIG. 1 has m rows memory units corresponding to m row decoding units, i.e., the row decoding unit 1, the row decoding unit 2, . . . , and the row decoding unit m. Each row decoding unit has a same structure. Referring to FIG. 2, a circuit schematic diagram of the row decoding unit 1 shown in FIG. 1 is provided in detail as an example.
The row decoding unit 1 shown in FIG. 2 includes: a pre-decoding unit 20 adapted for receiving an address signal, forming a selection signal based on the address signal, and providing the selection signal to a first level shift unit 211 and a control-gate line selection unit 23, where the selection signal is used to select a word line and a control-gate line of a memory unit which needs to be operated; the first level shift unit 211 adapted for receiving the selection signal, and outputting a first driving voltage VDDH1 or a second driving voltage VDDL1 based on the selection signal; a word line driving unit 221 including a PMOS transistor P1 and a NMOS transistor N1, adapted for receiving the first driving voltage VDDH1 or the second driving voltage VDDL1 output by the first level shift unit 211, and outputting a word line operation voltage to a word line WL1; the control-gate line selection unit 23 adapted for receiving the selection signal, selecting one of the control-gate lines connected to two memory bits of a same memory unit based on the selection signal, and outputting a first control signal and a second control signal to a second level shift unit 212 and a third level shift unit 213, respectively; the second level shift unit 212 adapted for receiving the first control signal, and outputting a third driving voltage VDDH2 or a fourth driving voltage VDDL2 based on the first control signal; a first control-gate line driving unit 222 including a PMOS transistor P2 and a NMOS transistor N2, adapted for receiving the third driving voltage VDDH2 or the fourth driving voltage VDDL2 output by the second level shift unit 212, and outputting a first control-gate line operation voltage to a first control-gate line CG1; the third level shift unit 213 adapted for receiving the second control signal, and outputting a third driving voltage VDDH2 or a fourth driving voltage VDDL2 based on the second control signal; and a second control-gate line driving unit 223 including a PMOS transistor P3 and a NMOS transistor N3, adapted for receiving the third driving voltage VDDH2 or the fourth driving voltage VDDL2 output by the third level shift unit 213, and outputting a second control-gate line operation voltage to the second control-gate line CG2.
However, referring to the dual-bit split gate flash memory array shown in FIG. 1, each row of memory units corresponds to a row decoding unit, which increases the area of the row decoding circuit. In addition, in order to reduce the area of the row decoding circuit, the areas of driving transistors (the PMOS transistor P2 and the NMOS transistor N2) of the first control-gate line driving unit 222 and driving transistors (the PMOS transistor P3 and the NMOS transistor N3) of the second control-gate line driving unit 223 in the row decoding unit 1, need to be reduced, whereby the driving speed of the memory array will inevitably be decreased. Therefore, a row decoding unit with a high speed and a low circuit area is needed.
More information about the conventional dual-bit split gate flash memory is disclosed in a Chinese patent application No. 201010217954, entitled “row decoding circuit for dual-bit split gate flash memory and method for operating the same”.